mirror of
https://github.com/Atmosphere-NX/Atmosphere.git
synced 2024-11-05 19:51:45 +00:00
commit
9a8aa0bc15
2 changed files with 53 additions and 32 deletions
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@ -82,15 +82,12 @@ void bootup_misc_mmio(void) {
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MC_SECURITY_CFG1_0 = 0;
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MC_SECURITY_CFG3_0 = 3;
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configure_default_carveouts();
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/* Mark registers secure world only. */
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if (exosphere_get_target_firmware() == EXOSPHERE_TARGET_FIRMWARE_100) {
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/* TODO: Switch these to use the enum. */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = 0x500244;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = 0xA3700000;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = 0x304;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = APB_SSER0_SATA_AUX | APB_SSER0_DTV | APB_SSER0_QSPI | APB_SSER0_SATA | APB_SSER0_LA;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG1_0 = APB_SSER1_SPI1 | APB_SSER1_SPI2 | APB_SSER1_SPI3 | APB_SSER1_SPI5 | APB_SSER1_SPI6 | APB_SSER1_I2C4 | APB_SSER1_I2C6;
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = 1 << 4 | 1 << 5 | APB_SSER2_DDS; /* bits 4 and 5 are not labeled in 21.1.7.3 */
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} else {
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/* Mark SATA_AUX, DTV, QSPI, SE, SATA, LA secure only. */
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG0_0 = APB_SSER0_SATA_AUX | APB_SSER0_DTV | APB_SSER0_QSPI | APB_SSER0_SE | APB_SSER0_SATA | APB_SSER0_LA;
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@ -114,37 +111,42 @@ void bootup_misc_mmio(void) {
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APB_MISC_SECURE_REGS_APB_SLAVE_SECURITY_ENABLE_REG2_0 = sec_disable_2;
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}
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/* reset Translation Enable Registers */
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MC_SMMU_TRANSLATION_ENABLE_0_0 = 0xFFFFFFFF;
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MC_SMMU_TRANSLATION_ENABLE_1_0 = 0xFFFFFFFF;
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MC_SMMU_TRANSLATION_ENABLE_2_0 = 0xFFFFFFFF;
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MC_SMMU_TRANSLATION_ENABLE_3_0 = 0xFFFFFFFF;
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MC_SMMU_TRANSLATION_ENABLE_4_0 = 0xFFFFFFFF;
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/* TODO: What are these MC reg writes? */
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MAKE_MC_REG(0x228) = 0xFFFFFFFF;
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MAKE_MC_REG(0x22C) = 0xFFFFFFFF;
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MAKE_MC_REG(0x230) = 0xFFFFFFFF;
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MAKE_MC_REG(0x234) = 0xFFFFFFFF;
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MAKE_MC_REG(0xB98) = 0xFFFFFFFF;
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
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MAKE_MC_REG(0x038) = 0xE;
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} else {
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MAKE_MC_REG(0x038) = 0x0;
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}
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MAKE_MC_REG(0x03C) = 0;
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/* MISC registers*/
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MAKE_MC_REG(0x9E0) = 0;
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MAKE_MC_REG(0x9E4) = 0;
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MAKE_MC_REG(0x9E8) = 0;
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MAKE_MC_REG(0x9EC) = 0;
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MAKE_MC_REG(0x9F0) = 0;
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MAKE_MC_REG(0x9F4) = 0;
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if (exosphere_get_target_firmware() >= EXOSPHERE_TARGET_FIRMWARE_400) {
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MAKE_MC_REG(0x01C) = 0;
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MC_SMMU_PTB_ASID_0 = 0;
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}
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MAKE_MC_REG(0x020) = 0;
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MAKE_MC_REG(0x014) = 0x30000030;
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MAKE_MC_REG(0x018) = 0x2800003F;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x034) = 0;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x030) = 0;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x010) = 1;
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(void)(MAKE_MC_REG(0x014));
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MC_SMMU_PTB_DATA_0 = 0;
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MC_SMMU_TLB_CONFIG_0 = 0x30000030;
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MC_SMMU_PTC_CONFIG_0 = 0x2800003F;
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_PTC_FLUSH_0 = 0;
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_TLB_FLUSH_0 = 0;
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_CONFIG_0 = 1; /* enable SMMU */
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(void)MC_SMMU_TLB_CONFIG_0;
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/* Clear RESET Vector, setup CPU Secure Boot RESET Vectors. */
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uint32_t reset_vec;
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@ -206,6 +208,7 @@ void setup_4x_mmio(void) {
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MAKE_MC_REG(0x660) = 0;
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MAKE_MC_REG(0x964) |= 1;
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CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD_0 &= 0xFFF7FFFF;
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/* TODO: What are these PMC scratch writes? */
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APBDEV_PMC_SECURE_SCRATCH51_0 = (APBDEV_PMC_SECURE_SCRATCH51_0 & 0xFFFF8000) | 0x4000;
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APBDEV_PMC_SECURE_SCRATCH16_0 &= 0x3FFFFFFF;
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@ -221,6 +224,7 @@ void setup_4x_mmio(void) {
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APBDEV_PMC_SECURE_SCRATCH102_0 = 0x0;
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APBDEV_PMC_SECURE_SCRATCH103_0 = 0x0;
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APBDEV_PMC_SECURE_SCRATCH39_0 = (APBDEV_PMC_SECURE_SCRATCH39_0 & 0xF8000000) | 0x88;
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/* TODO: Do we want to bother locking the secure scratch registers? */
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/* 4.x Jamais Vu mitigations. */
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/* Overwrite exception vectors. */
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@ -232,23 +236,27 @@ void setup_4x_mmio(void) {
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BPMP_VECTOR_UNK = BPMP_MITIGATION_RESET_VAL;
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BPMP_VECTOR_IRQ = BPMP_MITIGATION_RESET_VAL;
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BPMP_VECTOR_FIQ = BPMP_MITIGATION_RESET_VAL;
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/* Disable AHB arbitration for the BPMP. */
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AHB_ARBITRATION_DISABLE_0 |= 2;
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/* Set SMMU for BPMP/APB-DMA to point to TZRAM. */
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MC_SMMU_PTB_ASID_0 = 1;
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(void)(MAKE_MC_REG(0x014));
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_PTB_DATA_0 = 0x70012;
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MC_SMMU_AVPC_ASID_0 = 0x80000001;
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MC_SMMU_PPCS1_ASID_0 = 0x80000001;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x34) = 0;
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(void)(MAKE_MC_REG(0x014));
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MAKE_MC_REG(0x30) = 0;
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(void)(MAKE_MC_REG(0x014));
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_PTC_FLUSH_0 = 0;
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(void)MC_SMMU_TLB_CONFIG_0;
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MC_SMMU_TLB_FLUSH_0 = 0;
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(void)MC_SMMU_TLB_CONFIG_0;
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/* Wait for the BPMP to halt. */
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while ((FLOW_CTLR_HALT_COP_EVENTS_0 >> 29) != 2) {
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wait(1);
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}
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/* If not in a debugging context, setup the activity monitor. */
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if ((get_debug_authentication_status() & 3) != 3) {
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FLOW_CTLR_HALT_COP_EVENTS_0 = 0x40000000;
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@ -14,9 +14,22 @@ static inline uintptr_t get_mc_base(void) {
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#define MAKE_MC_REG(n) MAKE_REG32(MC_BASE + n)
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#define MC_SMMU_PTB_ASID_0 MAKE_MC_REG(0x01C)
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#define MC_SMMU_PTB_DATA_0 MAKE_MC_REG(0x020)
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#define MC_SMMU_AVPC_ASID_0 MAKE_MC_REG(0x23C)
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#define MC_SMMU_CONFIG_0 MAKE_MC_REG(0x010)
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#define MC_SMMU_TLB_CONFIG_0 MAKE_MC_REG(0x014)
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#define MC_SMMU_PTC_CONFIG_0 MAKE_MC_REG(0x018)
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#define MC_SMMU_PTB_ASID_0 MAKE_MC_REG(0x01C)
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#define MC_SMMU_PTB_DATA_0 MAKE_MC_REG(0x020)
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#define MC_SMMU_TLB_FLUSH_0 MAKE_MC_REG(0x030)
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#define MC_SMMU_PTC_FLUSH_0 MAKE_MC_REG(0x034)
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#define MC_SMMU_AFI_ASID_0 MAKE_MC_REG(0x238)
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#define MC_SMMU_AVPC_ASID_0 MAKE_MC_REG(0x23C)
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#define MC_SMMU_TRANSLATION_ENABLE_0_0 MAKE_MC_REG(0x228)
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#define MC_SMMU_TRANSLATION_ENABLE_1_0 MAKE_MC_REG(0x22C)
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#define MC_SMMU_TRANSLATION_ENABLE_2_0 MAKE_MC_REG(0x230)
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#define MC_SMMU_TRANSLATION_ENABLE_3_0 MAKE_MC_REG(0x234)
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#define MC_SMMU_TRANSLATION_ENABLE_4_0 MAKE_MC_REG(0xB98)
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#define MC_SMMU_PPCS1_ASID_0 MAKE_MC_REG(0x298)
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#define MC_SECURITY_CFG0_0 MAKE_MC_REG(0x070)
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