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Preliminary Exosphere FUSE driver
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hexkyz
parent
cc4f6f7f84
commit
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2 changed files with 328 additions and 0 deletions
143
exosphere/fuse.c
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143
exosphere/fuse.c
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#include <stbool.h>
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#include <stdint.h>
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#include <string.h>
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#include "fuse.h"
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#include "utils.h"
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#include "timers.h"
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/* Prototypes for internal commands. */
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void fuse_make_regs_visible(void);
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void fuse_enable_power(void);
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void fuse_disable_power(void);
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void fuse_wait_idle(void);
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/* Initialize the FUSE driver */
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void fuse_init(void)
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{
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fuse_make_regs_visible();
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/* TODO: Overrides (iROM patches) and various reads happen here */
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}
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/* Make all fuse registers visible */
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void fuse_make_regs_visible(void)
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{
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/* TODO: Replace this with a proper CLKRST driver */
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uint32_t* misc_clk_reg = (volatile uint32_t *)mmio_get_device_address(MMIO_DEVID_CLKRST) + 0x48;
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uint32_t misc_clk_val = *misc_clk_reg;
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*misc_clk_reg = (misc_clk_val | (1 << 28));
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}
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/* Enable power to the fuse hardware array */
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void fuse_enable_power(void)
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{
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FUSE_REGS->FUSE_PWR_GOOD_SW = 1;
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wait(1);
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}
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/* Disable power to the fuse hardware array */
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void fuse_disable_power(void)
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{
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FUSE_REGS->FUSE_PWR_GOOD_SW = 0;
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wait(1);
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}
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/* Wait for the fuse driver to go idle */
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void fuse_wait_idle(void)
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{
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uint32_t ctrl_val = 0;
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/* Wait for STATE_IDLE */
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while ((ctrl_val & (0xF0000)) != 0x40000)
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{
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wait(1);
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ctrl_val = FUSE_REGS->FUSE_CTRL;
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}
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}
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/* Read a fuse from the hardware array */
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uint32_t fuse_hw_read(uint32_t addr)
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{
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fuse_wait_idle();
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/* Program the target address */
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FUSE_REGS->FUSE_REG_ADDR = addr;
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/* Enable read operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x1; /* Set FUSE_READ command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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return FUSE_REGS->FUSE_REG_READ;
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}
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/* Write a fuse in the hardware array */
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void fuse_hw_write(uint32_t, value, uint32_t addr)
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{
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fuse_wait_idle();
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/* Program the target address and value */
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FUSE_REGS->FUSE_REG_ADDR = addr;
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FUSE_REGS->FUSE_REG_WRITE = value;
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/* Enable write operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x2; /* Set FUSE_WRITE command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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}
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/* Sense the fuse hardware array into the shadow cache */
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void fuse_hw_sense(void)
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{
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fuse_wait_idle();
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/* Enable sense operation in control register */
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uint32_t ctrl_val = FUSE_REGS->FUSE_CTRL;
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ctrl_val &= ~0x3;
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ctrl_val |= 0x3; /* Set FUSE_SENSE command */
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FUSE_REGS->FUSE_CTRL = ctrl_val;
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fuse_wait_idle();
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}
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/* Read the SKU info register from the shadow cache */
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uint32_t fuse_get_sku_info(void)
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{
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return FUSE_CHIP_REGS->FUSE_SKU_INFO;
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}
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/* Read the bootrom patch version from a register in the shadow cache */
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uint32_t fuse_get_bootrom_patch_version(void)
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{
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return FUSE_CHIP_REGS->FUSE_SOC_SPEEDO_1;
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}
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/* Read a spare bit register from the shadow cache */
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uint32_t fuse_get_spare_bit(uint32_t idx)
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{
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uint32_t spare_bit_val = 0;
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if ((idx >= 0) && (idx < 32))
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spare_bit_val = FUSE_CHIP_REGS->FUSE_SPARE_BIT[idx];
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return spare_bit_val;
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}
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/* Read a reserved ODM register from the shadow cache */
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uint32_t fuse_get_reserved_odm(uint32_t idx)
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{
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uint32_t reserved_odm_val = 0;
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if ((idx >= 0) && (idx < 8))
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reserved_odm_val = FUSE_CHIP_REGS->FUSE_RESERVED_ODM[idx];
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return reserved_odm_val;
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}
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185
exosphere/fuse.h
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185
exosphere/fuse.h
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#ifndef EXOSPHERE_FUSE_H
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#define EXOSPHERE_FUSE_H
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#include <stdbool.h>
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#include <stdint.h>
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#include "memory_map.h"
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/* Exosphere driver for the Tegra X1 FUSE registers. */
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typedef struct {
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uint32_t FUSE_CTRL;
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uint32_t FUSE_REG_ADDR;
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uint32_t FUSE_REG_READ;
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uint32_t FUSE_REG_WRITE;
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uint32_t FUSE_TIME_RD1;
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uint32_t FUSE_TIME_RD2;
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uint32_t FUSE_TIME_PGM1;
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uint32_t FUSE_TIME_PGM2;
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uint32_t FUSE_PRIV2INTFC;
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uint32_t FUSE_FUSEBYPASS;
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uint32_t FUSE_PRIVATEKEYDISABLE;
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uint32_t FUSE_DIS_PGM;
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uint32_t FUSE_WRITE_ACCESS;
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uint32_t FUSE_PWR_GOOD_SW;
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uint32_t _0x38[0x32];
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} fuse_registers_t;
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typedef struct {
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uint32_t FUSE_PRODUCTION_MODE;
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uint32_t _0x4;
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uint32_t _0x8;
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uint32_t _0xC;
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uint32_t FUSE_SKU_INFO;
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uint32_t FUSE_CPU_SPEEDO_0;
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uint32_t FUSE_CPU_IDDQ;
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uint32_t _0x1C;
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uint32_t _0x20;
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uint32_t _0x24;
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uint32_t FUSE_FT_REV;
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uint32_t FUSE_CPU_SPEEDO_1;
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uint32_t FUSE_CPU_SPEEDO_2;
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uint32_t FUSE_SOC_SPEEDO_0;
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uint32_t FUSE_SOC_SPEEDO_1;
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uint32_t FUSE_SOC_SPEEDO_2;
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uint32_t FUSE_SOC_IDDQ;
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uint32_t _0x44;
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uint32_t FUSE_FA;
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uint32_t _0x4C;
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uint32_t _0x50;
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uint32_t _0x54;
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uint32_t _0x58;
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uint32_t _0x5C;
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uint32_t _0x60;
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uint32_t FUSE_PUBLIC_KEY[0x8];
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uint32_t FUSE_TSENSOR_1;
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uint32_t FUSE_TSENSOR_2;
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uint32_t _0x8C;
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uint32_t FUSE_CP_REV;
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uint32_t _0x94;
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uint32_t FUSE_TSENSOR_0;
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uint32_t FUSE_FIRST_BOOTROM_PATCH_SIZE_REG;
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uint32_t FUSE_SECURITY_MODE;
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uint32_t FUSE_PRIVATE_KEY[0x4];
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uint32_t FUSE_DEVICE_KEY;
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uint32_t _0xB8;
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uint32_t _0xBC;
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uint32_t _0xC0;
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uint32_t FUSE_VP8_ENABLE;
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uint32_t FUSE_RESERVED_ODM[0x8];
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uint32_t _0xE8;
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uint32_t _0xEC;
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uint32_t FUSE_SKU_USB_CALIB;
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uint32_t FUSE_SKU_DIRECT_CONFIG;
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uint32_t _0xF8;
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uint32_t _0xFC;
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uint32_t FUSE_VENDOR_CODE;
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uint32_t FUSE_FAB_CODE;
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uint32_t FUSE_LOT_CODE_0;
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uint32_t FUSE_LOT_CODE_1;
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uint32_t FUSE_WAFER_ID;
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uint32_t FUSE_X_COORDINATE;
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uint32_t FUSE_Y_COORDINATE;
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uint32_t _0x11C;
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uint32_t _0x120;
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uint32_t FUSE_SATA_CALIB;
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uint32_t FUSE_GPU_IDDQ;
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uint32_t FUSE_TSENSOR_3;
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uint32_t _0x130;
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uint32_t _0x134;
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uint32_t _0x138;
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uint32_t _0x13C;
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uint32_t _0x140;
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uint32_t _0x144;
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uint32_t FUSE_OPT_SUBREVISION;
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uint32_t _0x14C;
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uint32_t _0x150;
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uint32_t FUSE_TSENSOR_4;
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uint32_t FUSE_TSENSOR_5;
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uint32_t FUSE_TSENSOR_6;
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uint32_t FUSE_TSENSOR_7;
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uint32_t FUSE_OPT_PRIV_SEC_DIS;
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uint32_t _0x168;
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uint32_t _0x16C;
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uint32_t _0x170;
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uint32_t _0x174;
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uint32_t _0x178;
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uint32_t _0x17C;
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uint32_t FUSE_TSENSOR_COMMON;
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uint32_t _0x184;
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uint32_t _0x188;
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uint32_t _0x18C;
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uint32_t _0x190;
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uint32_t _0x194;
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uint32_t _0x198;
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uint32_t _0x19C;
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uint32_t _0x1A0;
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uint32_t _0x1A4;
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uint32_t _0x1A8;
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uint32_t _0x1AC;
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uint32_t _0x1B0;
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uint32_t _0x1B4;
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uint32_t _0x1B8;
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uint32_t _0x1BC;
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uint32_t _0x1D0;
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uint32_t FUSE_TSENSOR_8;
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uint32_t _0x1D8;
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uint32_t _0x1DC;
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uint32_t _0x1E0;
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uint32_t _0x1E4;
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uint32_t _0x1E8;
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uint32_t _0x1EC;
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uint32_t _0x1F0;
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uint32_t _0x1F4;
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uint32_t _0x1F8;
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uint32_t _0x1FC;
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uint32_t _0x200;
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uint32_t FUSE_RESERVED_CALIB;
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uint32_t _0x208;
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uint32_t _0x20C;
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uint32_t _0x210;
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uint32_t _0x214;
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uint32_t _0x218;
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uint32_t FUSE_TSENSOR_9;
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uint32_t _0x220;
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uint32_t _0x224;
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uint32_t _0x228;
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uint32_t _0x22C;
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uint32_t _0x230;
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uint32_t _0x234;
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uint32_t _0x238;
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uint32_t _0x23C;
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uint32_t _0x240;
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uint32_t _0x244;
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uint32_t _0x248;
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uint32_t _0x24C;
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uint32_t FUSE_USB_CALIB_EXT;
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uint32_t _0x254;
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uint32_t _0x258;
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uint32_t _0x25C;
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uint32_t _0x260;
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uint32_t _0x264;
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uint32_t _0x268;
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uint32_t _0x26C;
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uint32_t _0x270;
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uint32_t _0x274;
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uint32_t _0x278;
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uint32_t _0x27C;
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uint32_t FUSE_SPARE_BIT[0x20];
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} fuse_chip_registers_t;
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#define FUSE_REGS ((volatile fuse_registers_t *)(mmio_get_device_address(MMIO_DEVID_FUSE) + 0x800))
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#define FUSE_CHIP_REGS ((volatile fuse_chip_registers_t *)(mmio_get_device_address(MMIO_DEVID_FUSE) + 0x900))
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void fuse_init(void);
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uint32_t fuse_hw_read(uint32_t addr);
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void fuse_hw_write(uint32_t, value, uint32_t addr);
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void fuse_hw_sense(void);
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uint32_t fuse_get_sku_info(void);
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uint32_t fuse_get_bootrom_patch_version(void);
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uint32_t fuse_get_spare_bit(uint32_t idx);
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uint32_t fuse_get_reserved_odm(uint32_t idx);
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#endif
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