TuxSH
|
067770334e
|
thermosphere: add fpu regs save/restore
|
2021-02-19 21:51:46 +00:00 |
|
TuxSH
|
a7741c8576
|
thermosphere: add cctx->userFrame
|
2021-02-19 21:51:46 +00:00 |
|
TuxSH
|
dd96c8b32b
|
thermosphere: fix ptimer time freezing (again)
|
2021-02-19 21:51:45 +00:00 |
|
TuxSH
|
68a1ce6dd2
|
thermosphere: properly implement guest timer stuff
|
2021-02-19 21:51:45 +00:00 |
|
TuxSH
|
388c245ce4
|
thermosphere: add TransportInterface abstraction layer
|
2021-02-19 21:51:45 +00:00 |
|
TuxSH
|
1086c0612c
|
thermosphere: refactor tegra uart code, etc.
|
2021-02-19 21:51:44 +00:00 |
|
TuxSH
|
8dc9be9f8e
|
thermosphere: pl011 uart refactor
|
2021-02-19 21:51:44 +00:00 |
|
TuxSH
|
018260645a
|
thermosphere: fix pl101 uart reg definitions
|
2021-02-19 21:51:44 +00:00 |
|
TuxSH
|
a6d191bf4b
|
thermosphere: add proper memory/instruction barriers for breakpoint stuff
|
2021-02-19 21:51:43 +00:00 |
|
TuxSH
|
1eb60a2a52
|
thermosphere: add hypervisor timer code
|
2021-02-19 21:51:43 +00:00 |
|
TuxSH
|
3d3a9925b9
|
thermosphere: qemu: get rid of arm tf
qemu impls psci anyway
|
2021-02-19 21:51:42 +00:00 |
|
TuxSH
|
501472324f
|
thermosphere: refactor exception handlers & add stolen time/emulated ptimer logic
|
2021-02-19 21:51:42 +00:00 |
|
TuxSH
|
b9d07fccd6
|
thermosphere: rewrite sysreg trapping code, add skeleton code for timer val trap handling; support A32 EL1 once again
|
2021-02-19 21:51:42 +00:00 |
|
TuxSH
|
d42d9e60b9
|
thermosphere: don't trap memory register writes/don't migrate sw breakpoints
Makes no sense on a system with ASLR
|
2021-02-19 21:51:41 +00:00 |
|
TuxSH
|
28552da099
|
thermosphere: vgic: largely reduce the number of mmio accesses
since we have to use 64 bits for VirqState anyway
|
2021-02-19 21:51:41 +00:00 |
|
TuxSH
|
d56185e432
|
thermosphere: make the pending virq list ordering stable
|
2021-02-19 21:51:41 +00:00 |
|
TuxSH
|
c42aef6ba7
|
thermosphere: fix wrong icfgr shift; fix list handling bug
|
2021-02-19 21:51:40 +00:00 |
|
TuxSH
|
03fe744bc4
|
thermosphere: vgic: fix OOB accesses, fix icfgr and itargetsr handling
qemu actually allows SPIs to use the N-N model
|
2021-02-19 21:51:40 +00:00 |
|
TuxSH
|
e49a035455
|
thermosphere: fix is/ic registers usage; fix offset calculation
|
2021-02-19 21:51:40 +00:00 |
|
TuxSH
|
0811572889
|
thermosphere: fix truncation in vgicCleanupPendingList
|
2021-02-19 21:51:39 +00:00 |
|
TuxSH
|
76a5e745e4
|
thermosphere: honor irq config for ppis
|
2021-02-19 21:51:39 +00:00 |
|
TuxSH
|
7130b6efd1
|
thermosphere: yikes
|
2021-02-19 21:51:39 +00:00 |
|
TuxSH
|
37b14bc4b8
|
thermosphere: use strict volatile bitfields just in case
|
2021-02-19 21:51:38 +00:00 |
|
TuxSH
|
13174e7458
|
thermosphere: vgic: fix critical bug in vgicUpdateState, add more checks
Yikes.
|
2021-02-19 21:51:38 +00:00 |
|
TuxSH
|
ef79908594
|
thermosphere: add CFI where needed, add PANIC macro, etc.
|
2021-02-19 21:51:38 +00:00 |
|
TuxSH
|
3a13ab2e46
|
thermosphere: vgic: mostly fix vSGI handling, remove unimplementable/unused stuff + bugfixes
Still somewhat broken, though
|
2021-02-19 21:51:37 +00:00 |
|
TuxSH
|
676a895cca
|
thermosphere: fix guest access to irq 25, etc; we don't need to raise VI manually
See Armv8a TRM "Virtual IRQ exception"
|
2021-02-19 21:51:37 +00:00 |
|
TuxSH
|
cdf3bc6942
|
thermosphere: add PPI definitions
|
2021-02-19 21:51:37 +00:00 |
|
TuxSH
|
fe0662a75d
|
vgic: fix multiple bugs
|
2021-02-19 21:51:36 +00:00 |
|
TuxSH
|
f3ad62d1b8
|
thermosphere: fix various vgic bugs; fix register access OOB bug (xzr)
|
2021-02-19 21:51:36 +00:00 |
|
TuxSH
|
27859a7541
|
thermosphere: vgic: fix enabled state of virqs
|
2021-02-19 21:51:36 +00:00 |
|
TuxSH
|
e3b6d64f1b
|
thermosphere: fix multiple bugs
|
2021-02-19 21:51:35 +00:00 |
|
TuxSH
|
c17b81aaf6
|
thermosphere: vgic code draft
|
2021-02-19 21:51:35 +00:00 |
|
TuxSH
|
176be2386d
|
thermosphere: also trap GICH (to deny access)
|
2021-02-19 21:51:35 +00:00 |
|
TuxSH
|
f9ec21e99e
|
thermosphere: handle stage2 data aborts, trap gicd accesses
|
2021-02-19 21:51:34 +00:00 |
|
TuxSH
|
1775d59977
|
thermosphere: implement stop point broadcast
|
2021-02-19 21:51:34 +00:00 |
|
TuxSH
|
b2c5ef2611
|
thermopshere: add "execute function" sgi
|
2021-02-19 21:51:34 +00:00 |
|
TuxSH
|
0b69407f8e
|
thermosphere: barrier & active core mask
|
2021-02-19 21:51:33 +00:00 |
|
TuxSH
|
0a9a8c2f15
|
thermosphere: handle physical IRQs
|
2021-02-19 21:51:33 +00:00 |
|
TuxSH
|
271d2a0ddb
|
thermosphere: add gicv2 register definitions
|
2021-02-19 21:51:33 +00:00 |
|
TuxSH
|
6289d2e398
|
thermosphere: sw breakpoint code, etc.
|
2021-02-19 21:51:32 +00:00 |
|
TuxSH
|
f8266775f6
|
thermosphere: remove breakpoint/watchpoint reg dump functions
|
2021-02-19 21:51:32 +00:00 |
|
TuxSH
|
83c6e2f0e7
|
thermosphere: add watchpoint + watchpoint merging code
|
2021-02-19 21:51:31 +00:00 |
|
TuxSH
|
9bc0ed2f70
|
thermosphere: refactor crt0 + watchpoint init
|
2021-02-19 21:51:31 +00:00 |
|
TuxSH
|
dc3f87a715
|
thermosphere: add actual breakpoint code
|
2021-02-19 21:51:31 +00:00 |
|
TuxSH
|
3649b94b5d
|
thermosphere: add breakpoint/watchpoint enable/reset code
|
2021-02-19 21:51:30 +00:00 |
|
TuxSH
|
a3da478089
|
thermopshere: refactor & fix single-stepping code
|
2021-02-19 21:51:30 +00:00 |
|
TuxSH
|
ff9714d4f6
|
thermopshere: refactor jump-to-kernel ,add single-step code
not working under qemu yet though
|
2021-02-19 21:51:30 +00:00 |
|
TuxSH
|
cc232ef4f8
|
thermosphere: add spinlock code
|
2021-02-19 21:51:29 +00:00 |
|
TuxSH
|
b742b861ab
|
thermometer: yeet most a32 support code 👌
|
2021-02-19 21:51:29 +00:00 |
|