8 commits

Author	SHA1	Message	Date
TuxSH	6be5b0a52f	Implement flush_dcache_all_tzram_pa and invalidate_icache_all_inner_shareable_tzram_pa for the crt0s	2018-02-28 19:06:41 +01:00
Michael Scire	c5b0639b8a	Implement BootConfig.	2018-02-27 20:28:34 -08:00
Michael Scire	0508ee29d8	Clean up SE TODOs, implement GIC nonsecure init	2018-02-27 19:58:56 -08:00
TuxSH	602507ee8f	Rename cache.s/.h to arm.s/.h	2018-02-27 22:29:47 +01:00
TuxSH	984ade3ede	Merge pull request #58 from MerryMage/context_id-rename ... Rename set_core_entrypoint_and_context_id	2018-02-26 22:26:46 +01:00
TuxSH	c7d83c6eb6	Rewrite the memory map-related code... ... ...other style fixes, etc.	2018-02-26 22:09:35 +01:00
MerryMage	3d40051146	Rename set_core_entrypoint_and_context_id	2018-02-26 17:11:49 +00:00
TuxSH	b0ea9c1a0b	Move source files to src/, add Makefile, fix all build and linkage errors, etc.	2018-02-25 20:00:50 +01:00

Renamed from exosphere/package2.c (Browse further)