28 commits

Author	SHA1	Message	Date
Michael Scire	366cc5e189	Exosphere: Fix extremely spooky Security Engine bugs, now makes it to the end of package2loader.	2018-05-21 04:30:53 -06:00
TuxSH	5b5d3c69c2	[exosphere] Fix bug in package2.c	2018-05-17 16:15:30 +02:00
TuxSH	05b8b42164	[exosphere] Rewrite crt0/init and ld script	2018-05-11 14:07:37 +02:00
Michael Scire	7ddf5a922c	Exosphere: Support unsigned/plaintext Package2s if signature is clear.	2018-04-11 21:56:30 -06:00
Michael Scire	c2eed3caf6	Integrate 5.x SMC API changes, add 4.x specific setup, implement target firmware selection	2018-03-25 15:05:08 -06:00
TuxSH	b35c418558	memcpy(x, NULL, 0) is undefined behavior	2018-03-08 11:17:46 +01:00
Michael Scire	3d8ff446ad	Implement BootReason config	2018-03-08 01:48:57 -08:00
TuxSH	03c1ad7119	Add most of warmboot_main	2018-03-03 19:31:22 +01:00
Michael Scire	661bcaa3ec	Change 'success' panic location to end of coldboot_main()	2018-03-02 15:09:51 -08:00
Michael Scire	102fb5004f	Cleanup TODOs, implement bootconfig SCR_EL3 bit setting	2018-03-02 15:04:16 -08:00
Michael Scire	301b166684	Implement CPU state init, fix bug in cpu_context restore	2018-03-02 14:16:54 -08:00
Michael Scire	ca7b441079	Add call to se_generate_stored_vector() before validating	2018-03-02 12:59:12 -08:00
Michael Scire	b3dbfd8ee0	Update pk2ldr outline, prepare for bootup_misc_mmio() impl	2018-03-02 11:28:05 -08:00
TuxSH	cad9cdc6e0	Reintroduce unmap_* in package2.c	2018-03-02 07:33:47 +01:00
Michael Scire	78bee60485	Fix dangling comments	2018-03-01 21:24:22 -08:00
Michael Scire	7b6d15ec36	Fix up package2.c, current build makes it to the panic() on hardware	2018-03-01 21:15:19 -08:00
TuxSH	63d0b08ac4	Rewrite relocation stuff	2018-03-02 02:47:19 +01:00
TuxSH	82f10b4320	Implements missings parts of pk2ldr, refactor relocation a bit	2018-03-01 19:11:09 +01:00
Michael Scire	9553c69c8f	Properly detect PK21 master key rev.	2018-03-01 03:28:34 -08:00
Michael Scire	205d3b8b80	Fix PK2LDR bugs, Fix SE bugs	2018-03-01 03:25:12 -08:00
TuxSH	6be5b0a52f	Implement flush_dcache_all_tzram_pa and invalidate_icache_all_inner_shareable_tzram_pa for the crt0s	2018-02-28 19:06:41 +01:00
Michael Scire	c5b0639b8a	Implement BootConfig.	2018-02-27 20:28:34 -08:00
Michael Scire	0508ee29d8	Clean up SE TODOs, implement GIC nonsecure init	2018-02-27 19:58:56 -08:00
TuxSH	602507ee8f	Rename cache.s/.h to arm.s/.h	2018-02-27 22:29:47 +01:00
TuxSH	984ade3ede	Merge pull request #58 from MerryMage/context_id-rename ... Rename set_core_entrypoint_and_context_id	2018-02-26 22:26:46 +01:00
TuxSH	c7d83c6eb6	Rewrite the memory map-related code... ... ...other style fixes, etc.	2018-02-26 22:09:35 +01:00
MerryMage	3d40051146	Rename set_core_entrypoint_and_context_id	2018-02-26 17:11:49 +00:00
TuxSH	b0ea9c1a0b	Move source files to src/, add Makefile, fix all build and linkage errors, etc.	2018-02-25 20:00:50 +01:00

Renamed from exosphere/package2.c (Browse further)