mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-11-27 19:12:01 +00:00
Add BIT instruction
This commit is contained in:
parent
19b8344568
commit
76ac31add6
2 changed files with 16 additions and 0 deletions
|
@ -141,6 +141,7 @@ namespace ChocolArm64
|
||||||
Set("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg));
|
Set("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg));
|
||||||
Set("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi, typeof(AOpCodeSimdImm));
|
Set("0x10111100000xxx<<x101xxxxxxxxxx", AInstEmit.Bic_Vi, typeof(AOpCodeSimdImm));
|
||||||
Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
|
Set("0x101110111xxxxx000111xxxxxxxxxx", AInstEmit.Bif_V, typeof(AOpCodeSimdReg));
|
||||||
|
Set("0x101110101xxxxx000111xxxxxxxxxx", AInstEmit.Bit_V, typeof(AOpCodeSimdReg));
|
||||||
Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
|
Set("0x101110011xxxxx000111xxxxxxxxxx", AInstEmit.Bsl_V, typeof(AOpCodeSimdReg));
|
||||||
Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
|
Set("0>101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg));
|
||||||
Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
|
Set("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd));
|
||||||
|
|
|
@ -33,6 +33,16 @@ namespace ChocolArm64.Instruction
|
||||||
}
|
}
|
||||||
|
|
||||||
public static void Bif_V(AILEmitterCtx Context)
|
public static void Bif_V(AILEmitterCtx Context)
|
||||||
|
{
|
||||||
|
EmitBitBif(Context, true);
|
||||||
|
}
|
||||||
|
|
||||||
|
public static void Bit_V(AILEmitterCtx Context)
|
||||||
|
{
|
||||||
|
EmitBitBif(Context, false);
|
||||||
|
}
|
||||||
|
|
||||||
|
public static void EmitBitBif(AILEmitterCtx Context, bool NotRm)
|
||||||
{
|
{
|
||||||
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
|
||||||
|
|
||||||
|
@ -47,6 +57,11 @@ namespace ChocolArm64.Instruction
|
||||||
|
|
||||||
EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
|
EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
|
||||||
|
|
||||||
|
if (NotRm)
|
||||||
|
{
|
||||||
|
Context.Emit(OpCodes.Not);
|
||||||
|
}
|
||||||
|
|
||||||
Context.Emit(OpCodes.And);
|
Context.Emit(OpCodes.And);
|
||||||
|
|
||||||
EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
|
EmitVectorExtractZx(Context, Op.Rd, Index, Op.Size);
|
||||||
|
|
Loading…
Reference in a new issue