mirror of
https://git.suyu.dev/suyu/sirit.git
synced 2024-12-22 20:22:02 +00:00
Add OpIAdd and OpBitwiseAnd
This commit is contained in:
parent
15a4d3c0d4
commit
d4c95981b5
3 changed files with 24 additions and 6 deletions
|
@ -262,11 +262,18 @@ class Module {
|
||||||
/// The least-significant bits will be zero filled.
|
/// The least-significant bits will be zero filled.
|
||||||
Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
|
Id OpShiftLeftLogical(Id result_type, Id base, Id shift);
|
||||||
|
|
||||||
|
/// Result is 1 if both Operand 1 and Operand 2 are 1. Result is 0 if either
|
||||||
|
/// Operand 1 or Operand 2 are 0.
|
||||||
|
Id OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2);
|
||||||
|
|
||||||
// Arithmetic
|
// Arithmetic
|
||||||
|
|
||||||
/// Unsigned-integer division of Operand 1 divided by Operand 2.
|
/// Unsigned-integer division of Operand 1 divided by Operand 2.
|
||||||
Id OpUDiv(Id result_type, Id operand_1, Id operand_2);
|
Id OpUDiv(Id result_type, Id operand_1, Id operand_2);
|
||||||
|
|
||||||
|
/// Integer addition of Operand 1 and Operand 2.
|
||||||
|
Id OpIAdd(Id result_type, Id operand_1, Id operand_2);
|
||||||
|
|
||||||
private:
|
private:
|
||||||
Id AddCode(std::unique_ptr<Op> op);
|
Id AddCode(std::unique_ptr<Op> op);
|
||||||
|
|
||||||
|
|
|
@ -11,11 +11,15 @@
|
||||||
|
|
||||||
namespace Sirit {
|
namespace Sirit {
|
||||||
|
|
||||||
Id Module::OpUDiv(Id result_type, Id operand_1, Id operand_2) {
|
#define DEFINE_BINARY(funcname, opcode) \
|
||||||
auto op{std::make_unique<Op>(spv::Op::OpUDiv, bound++, result_type)};
|
Id Module::funcname(Id result_type, Id operand_1, Id operand_2) { \
|
||||||
op->Add(operand_1);
|
auto op{std::make_unique<Op>(opcode, bound++, result_type)}; \
|
||||||
op->Add(operand_2);
|
op->Add(operand_1); \
|
||||||
return AddCode(std::move(op));
|
op->Add(operand_2); \
|
||||||
}
|
return AddCode(std::move(op)); \
|
||||||
|
}
|
||||||
|
|
||||||
|
DEFINE_BINARY(OpUDiv, spv::Op::OpUDiv)
|
||||||
|
DEFINE_BINARY(OpIAdd, spv::Op::OpIAdd)
|
||||||
|
|
||||||
} // namespace Sirit
|
} // namespace Sirit
|
|
@ -35,4 +35,11 @@ Id Module::OpShiftLeftLogical(Id result_type, Id base, Id shift) {
|
||||||
return AddCode(std::move(op));
|
return AddCode(std::move(op));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Id Module::OpBitwiseAnd(Id result_type, Id operand_1, Id operand_2) {
|
||||||
|
auto op{std::make_unique<Op>(spv::Op::OpBitwiseAnd, bound++, result_type)};
|
||||||
|
op->Add(operand_1);
|
||||||
|
op->Add(operand_2);
|
||||||
|
return AddCode(std::move(op));
|
||||||
|
}
|
||||||
|
|
||||||
} // namespace Sirit
|
} // namespace Sirit
|
Loading…
Reference in a new issue