CTCaer
84c5439c70
bdk: usb: utilize apb relaxed clocks for init
2024-06-02 07:01:31 +03:00
CTCaer
9a98c1afb9
bdk: stylistic corrections
...
And update copyrights
2023-02-11 23:46:38 +02:00
CTCaer
5bb9a244ea
bdk: utilize new gpio functions
2023-02-11 23:08:32 +02:00
CTCaer
d08fac5a08
bdk: xusb: improve clock deinit
...
Allows L4T to use XUSB on T210B01 after a UMS usage.
T210 somehow was fine.
2022-10-11 04:07:24 +03:00
CTCaer
70523e404f
bdk: whitespace refactor
2022-07-11 22:10:11 +03:00
CTCaer
b0c0a86108
bdk: migrate timers/sleeps to timer driver
2022-06-27 10:22:19 +03:00
CTCaer
258a343e21
bdk: usb: support deconfiguration of endpoints
...
TODO: Signal that to userspace and manage it.
2022-06-14 18:48:21 +03:00
CTCaer
f6c9e636d1
bdk: usb: improve USB2/XUSB power down
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TODO: add more power downs on XUSB stack
2022-06-14 18:46:46 +03:00
CTCaer
605f270f98
bdk: usb: fix a race condition in USB2 stack
...
When RAM is slow (no training), it's possible to have the stack failing to negotiate configuration successfully.
The race condition is caused by not flushing cache before sending a configuration packet reply.
Although, cache is write-through, this needs to happen.
2022-06-14 18:41:33 +03:00
CTCaer
7c74391754
bdk: bpmp: do not use full maintenance
...
Instead use proper clean/invalidation of dcache.
2022-02-15 00:14:14 +02:00
CTCaer
4914ce1d49
usb: add more timeout control for ep1 read/write finish
2021-08-28 17:00:23 +03:00
CTCaer
4949331f4c
usb: Rework timeouts
...
- Rework all timeouts to be more relaxed when doing big data transfers.
- Fix a bug where async transfer would timeout sooner instead of infinite tries.
Both showed up in Arch Linux, because of it's huge latency USB stack latency that can reach 1-2s.
The rework will let every OS work without adding additional wait time in the gadget loops.
2020-12-30 13:37:36 +02:00
CTCaer
a1188505e8
usb: Add XUSB support mainly for T210B01
2020-12-02 01:13:52 +02:00
CTCaer
b89bb35054
usb: Refactor some variables
2020-11-26 01:55:33 +02:00
CTCaer
caae685fab
usb: Add buffer alignment checks
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EDCI/EHCI controllers only allow 0x1000 aligned buffers.
So reply with a specific error type instead of a EP xfer error.
2020-11-26 01:54:10 +02:00
CTCaer
bd4517abab
usb: Name all controller errors
2020-11-26 01:50:49 +02:00
CTCaer
cabaa6cfb8
Utilize BIT macro everywhere
2020-11-26 01:41:45 +02:00
CTCaer
ab7a81081c
t210: Refactor AHB Gizmo registers
2020-11-15 14:46:42 +02:00
CTCaer
8a352bdfe2
usb: Split init into PHY init and device init
2020-11-15 14:45:48 +02:00
CTCaer
721e926a75
usb: Do proper UTMIPLL_HW_PWRDN_CFG0 config
2020-11-15 14:44:35 +02:00
CTCaer
0b314d7f21
clock: Move UTMIPLL init from USB to clock
2020-11-15 14:43:36 +02:00
CTCaer
8305058cf5
clock: Move PLLU init/deinit from USB to clock
2020-11-15 14:42:01 +02:00
CTCaer
6dddb968fa
usb: Fix various descriptor transfers in order to not rely on quirks
2020-11-15 14:38:18 +02:00
CTCaer
d3c318d0c9
usb: Correct latencies for HID gadgets
2020-11-15 14:37:14 +02:00
CTCaer
604ec4416d
usb: Refactor driver names and defines
2020-11-15 14:36:20 +02:00
CTCaer
c7fcea5f35
usb: Rfactor driver/gadgets in prep for XUSB
...
Allow gadgets using different USB controllers on demand.
This will allow plugging in XUSB for Mariko usage.
2020-11-15 14:30:25 +02:00
CTCaer
6a4161fdc4
usb: Move lang/serial descriptors to header
2020-11-15 14:04:10 +02:00
CTCaer
1f5b371608
Refactor some names
...
Additionally:
- Do not retry to init sd if all modes failed in Nyx.
- Do not try to read/write if sdmmc controller and card are not initialized.
2020-10-23 06:32:24 +03:00
CTCaer
1111125aab
usb: Invalidate cache on ep1_out_reading_finish
2020-08-15 12:15:02 +03:00
CTCaer
e158d9bc00
clk: Refactor CLK devices bits
2020-07-17 16:50:17 +03:00
CTCaer
6e256d29c7
Utilize hekate's BDK for hekate main and Nyx
2020-06-14 16:45:45 +03:00
CTCaer
185526d134
Introducing Bootloader Development Kit (BDK)
...
BDK will allow developers to use the full collection of drivers,
with limited editing, if any, for making payloads for Nintendo Switch.
Using a single source for everything will also help decoupling
Switch specific code and easily port it to other Tegra X1/X1+ platforms.
And maybe even to lower targets.
Everything is now centrilized into bdk folder.
Every module or project can utilize it by simply including it.
This is just the start and it will continue to improve.
2020-06-14 15:25:21 +03:00
