mirrors/hekate
1
0
Fork 0
mirror of https://github.com/CTCaer/hekate.git synced 2024-11-08 11:31:44 +00:00
Code Issues Releases Activity
1651 commits 2 branches 75 tags 6.7 MiB
Commit graph

458 commits

Author SHA1 Message Date
CTCaer
14c482ddce bdk: display: remove max77620 gpio 7 enable 
It is actually not used at all.
So do not configure it to save power.
 2024-06-05 15:20:27 +03:00
CTCaer
8d49bc3c33 bdk: hwinit: move LDO8 init in regulators init 
And also reorder it above I2C1 init (because of HOAG).
 2024-06-05 01:35:05 +03:00
CTCaer
39c614a3ab bdk: hwinit: move sd2 to hw init 
SD2 powers LDO0/1/8 on T210B01 so there's no need to be in display init.
Also there's not need to power it down first so configure it in one go.
 2024-06-05 01:33:15 +03:00
CTCaer
7652d9cdb1 bdk: display: use mipi cal sw war on T210 also 
As per Nvidia, the pad brick separates clock and data terminations.
This necessitates doing the calibration twice.

Nvidia/Nintendo probably never updated that part on T210 since it's from around
2015/2016. T210B01 is based on 2017 codebase so it has it.
HOS (nvservices, not boot) is probably updated to also do that.
If not, then they should fix it.

There are 0 known issue reports with that on T210, but well.
 2024-06-05 01:11:04 +03:00
CTCaer
48ef1826e9 bdk: display: rename functions 
display_init_framebuffer_pitch -> display_init_window_a_pitch
display_init_framebuffer_pitch_vic -> display_init_window_a_pitch_vic
display_init_framebuffer_pitch_inv -> display_init_window_a_pitch_inv
display_init_framebuffer_block -> display_init_window_a_block
display_init_framebuffer_log -> display_init_window_d_console
display_activate_console -> display_window_d_console_enable
display_deactivate_console -> display_window_d_console_disable
display_init_cursor -> display_cursor_init
display_set_pos_cursor -> display_cursor_set_pos
display_deinit_cursor -> display_cursor_deinit
 2024-06-05 01:00:58 +03:00
CTCaer
4fef1890aa bdk: rename exec_cfg to reg_write_array 
And cfg_op_t to reg_cfg_t.
 2024-06-05 00:49:15 +03:00
CTCaer
320b91a767 bdk: display: return duty for oled panel properly 
For display_get_backlight_brightness.
 2024-06-02 08:23:58 +03:00
CTCaer
c5f6837c35 bdk: display: wait 1 frame after display off cmd 2024-06-02 08:23:13 +03:00
CTCaer
72f980d0f4 bdk: display: fully streamline dc/win setup 
As explained before, Nvidia just grabbed the whole dynamic init and made arrays
of it, without actually optimizing it.
The second part of the streamline aims to fully de-duplicate that.
- Completely remove all already set registers for DC/DISP/WIN.
- Do not touch other windows when a specific window is setup.
- Init Window D also together with A/B/C since code is made for DISPA.
- Add missing increase for syncpt 1.
 2024-06-02 08:22:20 +03:00
CTCaer
b3be7e7a41 bdk: display: use the same HS exit threshold 
No need to use minimum on T210.
Use the same byte clocks as T210B01 to simplify init.
 2024-06-02 08:11:22 +03:00
CTCaer
26c6c6372d bdk: display: rename window setup arrays 
Add window number info and remove the fb naming
 2024-06-02 08:05:50 +03:00
CTCaer
28eb3f4bcd bdk: display: deduplicate array size macro 2024-06-02 08:02:44 +03:00
CTCaer
bd55a3e756 bdk: clock: always set DISPA source 
No need to distinguish between LP or HS.
Setting the same value doesn't glitch.
 2024-06-02 08:00:42 +03:00
CTCaer
b01cc2432f bdk: irq: remove ack source 
HW interrupts can't be managed by FIR.
Only actual hw can clear the interrupt.
 2024-06-02 07:46:18 +03:00
CTCaer
05db43a97c bdk: hwinit: move down debug uart init 2024-06-02 07:44:22 +03:00
CTCaer
859811a154 bdk: fatfs: update copyright 
Last edit was in 2022.
 2024-06-02 07:42:35 +03:00
CTCaer
6b54c4a477 bdk: usb: hid: don't send a packet if no new data 
Reduce the interrupt caused at the host side
 2024-06-02 07:40:11 +03:00
CTCaer
9d79af231e bdk: use static where it should 2024-06-02 07:09:34 +03:00
CTCaer
84c5439c70 bdk: usb: utilize apb relaxed clocks for init 2024-06-02 07:01:31 +03:00
CTCaer
8c44969afb bdk: blz: refactor style 2024-06-02 06:51:47 +03:00
CTCaer
7a74761da9 bdk: bpmp: add and use bpmp_clk_rate_relaxed 2024-06-02 06:51:06 +03:00
CTCaer
14706cef4e bdk: minerva: add emc src div disable 2024-06-02 06:46:28 +03:00
CTCaer
93296c2c38 bdk: joycon: add packet size checks 
Pass the real received data size and do the proper checks for minimum info.
 2024-05-19 17:42:10 +03:00
CTCaer
a070d2e394 bdk: ums: allow real sizes for boot partitions 
Since that's eMMC, do not clamp the size to 4MB.
That doesn't affect anything other than allowing the host to see the whole
physical partition .
 2024-05-19 10:57:20 +03:00
CTCaer
927489d2da bdk: add missed defines 2024-05-19 10:50:25 +03:00
CTCaer
ae29f359ee bdk: hwinit: rename reinit_workaround to deinit 2024-05-19 10:49:25 +03:00
CTCaer
7af343dd6c bdk: input: make joycon detection more robust 
There's a hw bug on the gpio controller that can latch the last value on reads.
Mitigate that by reading once to unlatch the input value.

Also actually allow sio to be polled every 8ms.
 2024-05-19 10:19:25 +03:00
CTCaer
547a3542ee bdk: display: add more defines 2024-05-19 10:16:52 +03:00
CTCaer
4bc0a0591c bdk: display: wait 2us for bl pwm config to take 
Fixes the tiny blink showing up while pwm is still at max.
 2024-05-19 10:15:52 +03:00
CTCaer
985c513770 bdk: hwinit: add arbiter config 2024-05-19 10:07:06 +03:00
CTCaer
16eb6a3c44 bdk: types: do not overflow on byte swaps 
Addresses warning message.
 2024-04-25 16:57:43 +03:00
CTCaer
856994e4f4 bdk: sprintf: add right padding support 2024-04-25 04:56:38 +03:00
CTCaer
ec2e62236a bdk: pinmux: add i2s pin config 2024-04-25 04:52:13 +03:00
CTCaer
2648a2655c bdk: sdram: add info about custom 8GB T210 config 
That's a suggestion on which 4GB modules are certainly fine to use.
 2024-04-25 04:50:07 +03:00
CTCaer
62153fdfbb bdk: types: add likely/unlikely global macros 2024-04-25 04:48:09 +03:00
CTCaer
28960728f9 bdk: joycon: add bit numbers on the button struct 2024-04-25 04:46:27 +03:00
CTCaer
902ccede9a bdk: joycon: use proper bits for batt levels 2024-04-25 04:45:50 +03:00
CTCaer
96efa7a002 bdk: vic: add support for P8 and R5G5B5 2024-04-25 04:44:22 +03:00
CTCaer
d92906db5e bdk: display: correct some reg names and add more 2024-04-25 04:44:08 +03:00
CTCaer
e8d6516f43 bdk: display: use basic profile for OLED 
That's the one with the accurate sRGB colors.
Anything else is over saturated.
 2024-04-25 04:38:57 +03:00
CTCaer
a6727f6e32 bdk: display: update active regs on vsync for WinD 
Doing that on hsync can cause issues on disable without actually syncing to it.
 2024-04-25 04:38:04 +03:00
CTCaer
e846f4576e bdk: minerva: l4t: adjust sdmmc1 la and freq table 
- LA is tightened up
- Copied frequencies are now 204/408/800/1333/1600/OC (from 204/666/800/1600/OC)
 2024-03-29 13:21:53 +02:00
CTCaer
42c02e97e8 bdk: display: add 6.2" panel clone 2024-03-29 13:21:53 +02:00
CTCaer
d687b53249 bdk: heap: add zalloc and utilize it 2024-03-27 09:00:53 +02:00
CTCaer
9e41aa7759 bdk: smmu: refactor and update driver 
- Allow ASID to be configured
- Allow 34-bit PAs
- Use special type for setting PDE/PTE config
- Initialize all pages as non accessible
- Add function for mapping 4MB regions directly
- Add SMMU heap reset function
- Correct address load OP to 32-bit and remove alignment on SMMU enable payload
- Refactor all defines
 2024-03-14 09:21:06 +02:00
CTCaer
9ba7c44b89 bdk: clock: use real source clock dividers 
Use CLK_SRC_DIV macro in order to have the actual divider showing.
 2024-03-13 02:01:01 +02:00
CTCaer
9a520d63a6 bdk: smmu: refactor driver and allow other asid 2024-03-13 01:54:46 +02:00
CTCaer
20e661fc01 bdk: refactor flow control defines 2024-03-13 01:50:45 +02:00
CTCaer
3a4fa12f42 bdk: smmu: powergate ccplex after enabling smmu 2024-03-13 01:44:58 +02:00
CTCaer
fb31cb2926 bdk: ccplex: add no rst vector lock & powergating 
Allow not locking the reset vectors and launch a new payload after powergating ccplex.
 2024-03-13 01:37:52 +02:00